To access an information stored in a chip, conventionally, it requires extra power supplied and a sophisticated installation on tester, for example a probing card (or any other equipment) which may cause inconvenience. In addition, a manual touch or a machine contact would induce electrostatic discharge (ESD) damage for the chip.
Tracking information through controlled collapse chip connection (C4)/through substrate via (TSV) increases area penalty (extra layout of power/ground/signals on C4/TSV), and once one of the connections fails, the information is unreadable.
3DIC comprises a plurality of stacked chips provided from different companies or processes, and needs complete information recorded and being freely written/read, and the complete information comprises: company information, wafer tracking information (e.g., fabrication, process, part name and die-location), chip specification (test condition/setup and/or test results/parameters), and testing execution. Thus, there is a need to solve the above-mentioned problems.